1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, it relates to a semiconductor device having an insulating film and an interfacial insulating film, and a method for manufacturing the same.
2. Description of the Related Art
In recent years, with regard to semiconductor integrated circuits, their miniaturization has been advanced, particularly as for multilayer interconnections in logic circuits. When intervals between metals of the multilayer interconnections are fine, capacitance between adjacent interconnections increases, which leads to the deterioration of electric signal speed and which also gives rise to crosstalk (which is a phenomenon that another signal functions as noise).
As one means for preventing the above-mentioned problem, there has been adopted the practice of lowering the dielectric constant of the insulating film between metal layers, and nowadays, much attention has been paid to the change from a silicon oxide film formed by a conventional plasma CVD method (the dielectric constant=4.3) (hereinafter referred to as xe2x80x9cthe p-SiO2 filmxe2x80x9d) to a fluorine doped plasma silicon oxide film (the dielectric constant=2.8 to 4.3) (hereinafter referred to as xe2x80x9cthe p-SiOF filmxe2x80x9d).
When fluorine concentration in the p-SiOF film is increased, its dielectric constant can be lowered, but if the fluorine concentration is excessively increased, its moisture resistance deteriorates. Therefore, at fluorine concentrations that the moisture resistance does not deteriorate, the dielectric constant cannot sufficiently be lowered (the dielectric constant about 3.3).
In order to solve the above-mentioned problem, the prior art has proposed increasing the density of a plasma itself, see, for example, SSDM, p. 157 (1995).
While this suggested technique can increase the fluorine concentration more than a conventional technique, when the fluorine concentration reaches a certain level deterioration of the film occurs. For this reason, the dielectric constant cannot be lowered significantly.
When p-SiOF film is used in a device, it is essential to flatten the film, however if a chemical machine polishing method (hereinafter referred to as xe2x80x9cCMPxe2x80x9d) is used for flattening the p-SiOF film, the above-mentioned problem of deterioration of moisture resistance occurs. As a consequence, when CMP is used, further increase of the dielectric constant cannot be avoided.
As described above, the employment of CMP in a p-SiOF process has heretofore presented problems.
Two conventional examples using CMP will be described.
In one conventional example, a p-SiOF film is directly formed on a metal as shown in FIGS. 3(a)-3(c). For example, as described in Japanese Patent Application Laid-open No. 333919/1994, a first metal 301 is formed, and a p-SiOF film 302 having a dielectric constant of 3.0 and a fluorine concentration of 7xc3x971021 atoms/cc in the wafer surface is then formed thereon by the use of three gases of SiF4, 02 and Ar in accordance with an ECR-CVD method. If CMP is carried out to flatten this film, the film absorbs water, so that the dielectric constant of the film increases.
In a worse case, a large amount of introduced fluorine (F) whose bond is weak reacts with H2O to produce HF, with the result that corrosion of the metal and dissolution of the metal takes place. Here, reference will be made to a case where a fluorine concentration is lowered to about 1.0xc3x971021 atoms/cc.
After CMP processing, the film is as shown in FIG. 3(b). Next, the film is coated with a photoresist, and alignment exposure is then carried out to pattern the photoresist. Afterward, an etching technique, i.e., a magnetron RIE technique using C4F8, CO and an Ar gas is utilized to form holes.
Furthermore, after the formation of TiN, blanket WCVD is carried out to form a metal via 303 by a process which is called etch back. Afterward, continuous sputtering of a second metal 304 such as AlCu-TiN is done, and it is then patterned by the photoresist. This serial operation is carried out once or more to form multilayer interconnections as shown in FIG. 3(c).
A problem of this process is that when the fluorine concentration in the p-SiOF film is high, the film absorbs moisture during CMP processing of the film and when the fluorine concentration in the film is low, dielectric constant increases.
In a next example, an SiO2 film is sandwiched between upper and lower p-SiOF films to inhibit the hygroscopicity of the p-SiOF films. In Japanese Patent Application Laid-open No. 9372/1995, there has been described an SiOF film formed in a tetraethoxy orthosilicate system (hereinafter referred to as xe2x80x9cthe TEOS systemxe2x80x9d), and therefore, description will be made with reference to this technique. FIGS. 4(a)-4(c)xe2x80x2 shows its flow diagram.
According to the suggested method, after the formation of a first metal 401, a first p-SiO2 film 402 is formed, and a TEOS system material with which a fluorine containing gas is mixed is then used to form a fluorine doped SiO2 film (a p-SiOF film 403). Afterward, a second p-SiO2 film 404 is formed thereon.
Here, the plasma SiOF film is formed by a high density plasma CVD method which is preferred for moisture resistance, particularly a plasma SiO2 film high density plasma CVD method.
In a conventional example, parallel plate type plasma CVD has been used, but in this example, the laminated film is formed by a high density plasma CVD method.
Here, fluorine concentration in the SiOF film is 7xc3x971021 atoms/cc. After the first metal 401 has been formed, the continuous growth of SiO2/SiOF/SiO2 is carried out by high density plasma CVD, whereby a structure as shown in FIG. 4(a) or FIG. 4(a)xe2x80x2 is obtained. In the case that the p-SiOF film 403 which is an intermediate layer is relatively thick as shown in FIG. 4(a), the p-SiOF film 403 is exposed as in FIG. 4(b), after the CMP processing has been made. Although the p-SiOF film has already been sandwiched between the p-SiO2 films in order to control hygroscopicity of the p-SiOF, the p-SiOF film 403 is exposed, and as a result, the film absorbs water during CMP, processing. As a consequence, the dielectric constant of the film increases.
In order to avoid the above-mentioned problems, the p-SiOF film 403 can be formed relatively thin and the second SiO2film 404 can be formed relatively thick as in FIG. 4(a)xe2x80x2, and in such case, the p-SiOF film 403 will not be exposed after CMP processing, as shown in FIG. 4(b)xe2x80x2. In such case, however, the p-SiO2 film may invade the adjacent metal layer, so that increase of the dielectric constant occurs.
Afterward, as in the above-mentioned example, the via hole formation, the metal via formation and the second metal formation are done in this order, so that multilayer interconnections maybe formed as in FIG. 4(c) or FIG. 4(c)xe2x80x2.
FIG. 5 shows the relation between fluorine content in the fluorine-doped silicon oxide film and the dielectric constant in the case where high density plasma CVD is used, and FIG. 6 shows the relation between fluorine content in the fluorine doped silicon oxide film and hygroscopicity in the case where high density plasma CVD is used (Semiconductor Integrated Circuit Symposium Manuscript in 1995, p. 45). These drawings illustrate the relationship between fluorine content in the silicon oxide film and dielectric constant and the relationship between fluorine content and hygroscopicity. The actual values of fluorine content and these characteristics may depend slightly on the actual selected device, and so they are not always constant, but these drawings still show the influence of fluorine content in the silicon oxide film on dielectric constant and hygroscopicity.
The first problem is that in both of the above examples as dielectric constant increases, the via holes become abnormal and metal corrosion occurs, when the p-SiOF film having a low dielectric constant is subjected to CMP processing. This reason is that p-SiOF film having the low dielectric constant absorbs water when exposed to water, so that dielectric constant increases and the resistance of the via holes become abnormal, and the absorbed water reacts with fluorine to bring about metal corrosion.
The second problem is that when the p-SiOF film which is the intermediate of the SiO2/SiOF/SiO2 structure is formed relatively thin so as to solve the first problem or the second example, the dielectric constant between the metallic layers increases. This reason is that a ratio of p-SiO2 occupied between the metallic layer is relatively high.
Objects of the present invention are to prevent the increase of capacitance between layers in a multilayer interconnection structure of a semiconductor integrated circuit (the lowering of the dielectric constant) and to improve reliability by minimizing via hole resistance.
The present invention provides a semiconductor device which comprises a plurality of interconnections formed on a semiconductor substrate, a first fluorine doped silicon oxide film for filling up spaces between the plurality of interconnections, and a second fluorine doped silicon oxide film which is formed on the first fluorine doped silicon oxide film and which has a flattened surface and which is free from hygroscopicity.
This application is based on application No. Heisei 8-140003/1996 filed Jun. 3, 1996 in Japan, the contents of which are incorporated herein by reference.